Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
802.11n (MIMO WLAN) LDPC decoder / encoder
特色
- Code length: 648, 1296, 1944.
- Code rates: 1/2, 2/3, 3/4, 5/6 (for each code length).
- Programmable number of iterations.
- Internal convergence test stops the decoder when data is fully recovered (0 errors), to save power and increase throuhgput.
- High throughput support - up to 360Mbps.
- encoder included
- Code synthesizable to ASIC and FPGA.
可交付内容
- Verilog/VHDL source code or verilog EDIF netlist.
- Extensive testing environment (test bench + stimuli generator).
- Matlab model.
- Synthesis script for Synopsys Design Compiler
- Detailed documentation.
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