MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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800G Low Latency Level3 Memory Sub System
特色
- Proven 800G Performance
- Supports AXI4 Interface for configuration
- Supports Various Vendors(Synopsys/Micron/Samsung/Xilinx) Memory Marcos
- Low Latency
- Supports memory interfaces of 8 to 128bits in 4 bit increments
- Supports Configurable Data rates
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