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64G/56G SerDes
The Innosilicon 64G/56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, the PHY has been configured to support 64G/56G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics and backplanes with the built-in low-jitter LC PLL and CDR to optimize the signal integrity. The Innosilicon 56G Long Reach Serdes solution meets the functionality, power, performance and area requirements of a variety of network applications.
The PHY is fully compliant with the following standards: PCIE6/5, IEEE 802.3 and OIF, CEI-56G+ LR PAM-4, CEI-25G+ LR/MR NRZ, JESD204C/B (25/32G), 10GKR/100G KR-4 LR, 400GAUI-8 LR/MR, CEI11G-LR.
The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics and backplanes with the built-in low-jitter LC PLL and CDR to optimize the signal integrity. The Innosilicon 56G Long Reach Serdes solution meets the functionality, power, performance and area requirements of a variety of network applications.
The PHY is fully compliant with the following standards: PCIE6/5, IEEE 802.3 and OIF, CEI-56G+ LR PAM-4, CEI-25G+ LR/MR NRZ, JESD204C/B (25/32G), 10GKR/100G KR-4 LR, 400GAUI-8 LR/MR, CEI11G-LR.
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65G/56G SerDes IP
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