MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
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64 State 4x8PSK (4D 8PSK) CCSDS ECSS Viterbi Decoder IP Core
The 64 State 4x8PSK (4D 8PSK) CCSDS ECSS Viterbi Decoder is a fully parallel 64 state error control decoder using the maximum likelihood Viterbi algorithm for the 4x8PSK (4D 8PSK) multi-dimensional trellis code specified in the CCSDS and ECSS standards.
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