MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
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64-bit RISC-V core with out-of-order pipeline based complex for Linux-based embedded systems
64-bit RISC-V core with out-of-order pipeline based complex.
Maximum performance for running Linux high-end applications.
Maximum performance for running Linux high-end applications.
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Block Diagram of the 64-bit RISC-V core with out-of-order pipeline based complex for Linux-based embedded systems
64-bit Processor IP
- 64-bit RISC-V Multi-Core Linux-Capable processor
- Ultra High Performance 64-bit RISC-V Embedded Processor
- High Performance 64-bit RISC-V Multi-Core Application Processor
- 64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN
- 64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
- 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension