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6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
特色
- Ultra High Density 7% up to 15% denser after P&R compared to standard 7-Track library
- Pulsed latches as Spinner Cells instead of D-flip-flops: for min. 30% gain in density
- Metal layer 2 available for routing as only
- Metal 1 used for cell design
- 6-Track cells for optimal area reduction
- Power reduction features
- 30% less power consumption versus 7-Track library at nominal voltage
- Low Voltage Capability for additional power savings when operating down to 1.0 V +/-10%
- Smooth implementation
- Pulse generation automated by the script for Insert pulse generation
- Spinner cell design minimizing hold time violations
- Optimal Design for Yield
- Design methodology ensuring High-Yield circuits despite Mismatch
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standard cell IP
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 7 track Ultra High Density standard cell library at TSMC 28 nm
- 7 track Ultra High Density standard cell library at TSMC 28 nm HPC+