MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
56Gbps LR SerDes IP on TSMC 16/12nm
Features include the lowest power in the industry, excellent insertion loss handling for communication applications; high-performance supply noise immunity for SoC integration.
查看 56Gbps LR SerDes IP on TSMC 16/12nm 详细介绍:
- 查看 56Gbps LR SerDes IP on TSMC 16/12nm 完整数据手册
- 联系 56Gbps LR SerDes IP on TSMC 16/12nm 供应商