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56G-LR Pam4 SerDes
56G LR SerDes PHY provides exceptional performance w/ best-in-class power & area, making it ideal for machine learning and 5G infrastructure apps
The Cadence 56Gbps Long Reach Quad-Lane SerDes IP for TSMC 7nm operates at a full-rate of 56Gbps using PAM-4 modulation, as well as 28/10Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The area- and power-optimized design is ideal for high port-density applications that require long-reach and medium-reach links.
The Cadence 56Gbps Long Reach Quad-Lane SerDes IP for TSMC 7nm operates at a full-rate of 56Gbps using PAM-4 modulation, as well as 28/10Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The area- and power-optimized design is ideal for high port-density applications that require long-reach and medium-reach links.
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Serdes IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency