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5.8GHz Fractional-N PLL synthesizer
130GF_PLL_02 is intended for SoC clock generation with support of BFSK modulation up to 4Mbps output data rate. PLL IP block embeds a reference 8MHz/16MHz/ 32MHz/64MHz XTAL oscillator, which is able to work as an input signal buffer in the same frequency range.
The internal 5.725GHz-5.875GHz high frequency VCO provides both excellent phase noise performance and ultra-fine frequency tuning step.
Quadrature former is intended to generate differential output signals with phase shift 90°, coherent to input signal.
The internal 5.725GHz-5.875GHz high frequency VCO provides both excellent phase noise performance and ultra-fine frequency tuning step.
Quadrature former is intended to generate differential output signals with phase shift 90°, coherent to input signal.
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PLL IP
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