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5.5 Volt Comparator with Programmable Thresholds on TSMC 40nm
The S3DACMPT40 combines low-power comparator where the programmable threshold is implement using digital-to analog converter (DAC) which drive the comparator inverting input so the that individual trip threshold can be digitally set. Each programmable threshold is also available externally by means of interchanging them with the comparator inputs. During sampling phase, a capacitor of TBD pf is switched to the input line in order to have near infinite impedance.
This 8-bit Voltage DAC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL.
This 8-bit Voltage DAC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL.
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Block Diagram of the 5.5 Volt Comparator with Programmable Thresholds on TSMC 40nm
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