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32-bit SSRAM/PROM Controller
The 32-bit SSRAM/PROM Controller IP cores is an 32-bit SSRAM/PROM/IO controller that interfaces
external Synchronous pipelined SRAM, PROM, and I/O to the AMBA AHB bus. The controller acts as a slave on the AHB bus and has a configuration register accessible through an APB slave interface.
external Synchronous pipelined SRAM, PROM, and I/O to the AMBA AHB bus. The controller acts as a slave on the AHB bus and has a configuration register accessible through an APB slave interface.
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