32-bit Multiprocessor with Level-2 Cache-Coherence
The A25MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. Andes Coherence Unit (ACU) manages level-1 cache coherence including I/O coherence for cacheless bus masters, and duplicated L1 tag to screen allocated lines for snoop queries. Other A25MP features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality improvement, and QuickNap™, PowerBrake, and WFI for power management.
查看 32-bit Multiprocessor with Level-2 Cache-Coherence 详细介绍:
- 查看 32-bit Multiprocessor with Level-2 Cache-Coherence 完整数据手册
- 联系 32-bit Multiprocessor with Level-2 Cache-Coherence 供应商