MIPI D-PHY Tx-Only 4 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
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32 Bit - Embedded RISC-V Processor Core
The L31(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registers.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L31 and to generate corresponding hardware and software development kits.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L31 and to generate corresponding hardware and software development kits.
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Block Diagram of the 32 Bit - Embedded RISC-V Processor Core
Processor IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- Secure-IC Securyzr(TM) Cyber Escort Unit IP provides real time detection of sero day attacks on processor
- 64-bit RISC-V Application Processor Core
- 64-bit RISC-V Application Processor Core