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32:1 serializer followed by sub-LVDS drivers
The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data. The LVDS drivers operate in subLVDS mode only, which is defined in the CCP2 standard. Each LVDS driver has a programmable on-die termination resistor to facilitate high frequency operation, and supports test data output mode. The LSB of 32-bit data is sent first. The clock for the serializer is generated using a local PLL. The maximum data rate for the transmitter is 960Mb/s.
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32:1 serializer followed by sub-LVDS drivers IP
- Sub-LVDS receiver followed by 1:4 de-serializer
- Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
- Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
- Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
- Cortus Development Platform with Spartan-6 X75 FPGA with 1 Mbyte of SRAM