USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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3.3V with 5V IO Linear bond(EmFlash Process)
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Customized I/Os IP
- Integrated ESD cell designs for General I/O, eMMC I/Os, SDIOs, and ONFI I/O(12nm~180nm)
- Digital and Analog I/O for RF Application
- Low power 32KHz crystal oscillator I/O pad by TSMC 0.18um Logic power 1P6M process
- 2.5/3.3V I/O Compatible with PCIX 1.0, Stagger, 1P5M
- 2.5/3.3V I/O Compatible with PCIX 1.0, Stagger, 1P5M
- 2.5/3.3V I/O Compatible with DDR266 & SDRAM, Stagger, 1P5M