MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
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3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
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