USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
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3.3V to 0.3V and VCCK-0.3V / 10mA voltage source for N/P well forward body bias, Linear Regulator, UMC 55nm uLP/RVT Low-K Logic Process
3.3V to 0.3V and VCCK-0.3V / 10mA voltage source for N/P well forward body bias, Linear Regulator, UMC 55nm uLP/RVT Low-K Logic Process
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