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3.3V general purpose I/O for 28nm CMOS
The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
By default, a 2kV HBM ESD protection is included. This is however easily scaled to any desired level.
This specific IP macro is designed in TSMC 28nm RF HPC+ MMWave, and can be ported to other technologies upon request using Sofics inhouse design tool flow.
Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
By default, a 2kV HBM ESD protection is included. This is however easily scaled to any desired level.
This specific IP macro is designed in TSMC 28nm RF HPC+ MMWave, and can be ported to other technologies upon request using Sofics inhouse design tool flow.
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Block Diagram of the 3.3V general purpose I/O for 28nm CMOS
