Deeply Embedded AI Accelerator for Microcontrollers and End-Point IoT Devices
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2D图像缩放IP核
2D图像缩放IP核将一种输入视频帧大小转换成另一种输出视频帧大小。其灵活的架构支持各种缩放比例的算法。高度可配置的设计利用了莱迪思FPGA中的嵌入式DSP块。简单的I/O握手协议使得内核适用于视频流或者突发的输入视频数据处理。可按每帧对在系统输入和输出帧大小进行更新。
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Block Diagram of the 2D图像缩放IP核
FPGA IP
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Ethernet TSN Switch IP Core - Efficient and Massively Customizable
- CXL 2.0 Agilex FPGA Acclerator Card
- PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
- 65nm/40nm Low Power eFPGA IP and Open Source FPGA Software