The 25Gbps 64-bit Ethernet IP solution offers a fully integrated IEEE P802.3by compliant package for NIC (Network Interface Card) and Ethernet switching applications. This ultra-low latency solution is specifically targeted for demanding financial, high frequency trading and HPC applications.
* Round Trip Latency of 59.6ns + Device Specific Transceiver Latency
As shown in the figure below, the 25Gbps Ethernet IP includes:
* Ultra-Low latency MAC; Tx = 17.4ns , Rx = 17.4ns; (64-bit user interface mode)
* Ultra-Low latency PCS; Tx = 12.4ns , Rx = 12.4ns; (64-bit user interface mode)
* Technology dependent transceiver wrapper for Altera and/or Xilinx FPGAs
* Statistics counter block (for RMON and MIB)
* MDIO and I2C cores for external module and optical module status/control
- MAC Core Features
- Implements the full P802.3by specification with preamble/SFD generation, frame padding generation, CRC generation and checking on transmit and receive respectively.
- Implements 802.3bd specification with ability to generate and recognize PFC pause frames.
- Implements reconciliation sublayer functionality with start and terminate control characters alignment, error control character and fault sequence insertion and detection.
- PCS layer 25GMII interface implemented as 64-bit (single data rate) SDR.
- Deficit Idle Count (DIC) mechanism to ensure data rates of 25Gbps at the transmit interface.
- Optional padding of frames if the size of frame is less than 64 bytes.
- Implements fully automated XON and XOFF Pause Frame (802.3 Annex 31A) generation and termination providing flow control without user application intervention. Non PFC Mode only with use of support wrapper containing Rx User Interface Buffer.
- Pause frame generation additionally controllable by user application offering flexible traffic flow control.
- Support for VLAN tagged frames according to IEEE 802.1Q.
- Support any type of Ethernet Frames such as SNAP / LLC, Ethernet II/DIX or IP traffic.
- Discards frames with mismatching destination address on receive (except Broadcast and Multicast frames).
- Programmable Promiscuous mode support to omit MAC destination address checking on receive path.
- Optional multicast address filtering with 64-bit Hash Filtering table providing imperfect filtering to reduce load on higher layers.
- High speed CRC-32 generation and checking.
- Optional prevention of CRC appending in frame data by MAC to allow CRC to be pre-embedded in frame data by user application.
- Optional insertion of error control character in transmitted frame data.
- Optional forwarding of the CRC field to user application interface.
- Programmable frame maximum length providing support for any standard or proprietary frame length (e.g. 9K-Bytes Jumbo Frames).
- Status signals available with each Frame on the user interface providing information such as frame length, VLAN frame type indication and error information.
- Optional padding termination on RX path for NIC applications or forwarding of unmodified data to the user interface.
- Optional internal 25GMII Loop-back with use of support wrapper containing 25GMII Loop-back Buffer.
- Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames.
- Altera Avalon or Xilinx AXI4 interface compliant user interface with use of support wrapper containing Tx and Rx User Interface Buffers.
- Implements statistics and event signals providing support for 802.3 basic and mandatory managed objects as well as IETF Management Information Database (MIB) package (RFC 2665) and Remote Network Monitoring (RMON) required in SNMP environments.
- PCS Core Features
- Implements 25GBase-R PCS core compliant with IEEE P802.3by Specifications.
- Implements a 64-bit 25GMII interface to operate at 25Gbps for 25G Ethernet.
- Implements 64b/66b encoding/decoding for transmit and receive PCS using 802.3-2015 specified control codes.
- Implements 25G scrambling/descrambling using 802.3-2008 specified polynomial 1 + x39 + x58.
- Ability to generate scrambled idle test pattern compliant with IEEE P802.3by Specifications.
- Implements 66-bit block synchronization state machine as specified in 802.3-2008 specifications.
- Automatic clock compensation without the need for Inter Packet Gap (IPG) insertion/deletion that is achieved with use of support wrapper containing Rx
- 25GMII Buffer.
- Implements gear-box logic to convert 66-bit blocks to 64-bit for line side. The 64-bit interface operates at the transceiver user clock.
- Implements Bit Error Rate (BER) monitor compliant with IEEE P802.3by Specifications. In addition, the core implements various status and statistics required by the IEEE 802.3-2008 such as block synchronization status and test mode error counter.
- Implements optional 25GMII remote loopback to loopback data received from Rx PCS back to Tx PCS with use of support wrapper containing 25GMII remote loop-back Buffer.