MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
25G Ethernet MAC and PCS + RS-FEC
The IP core can support full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.
The core includes Reed Solomon FEC RS(528, 514, 10) with FEC bypass and error correction bypass capabilities. A second option of the IP core without RS-FEC is also available.
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Block Diagram of the 25G Ethernet MAC and PCS + RS-FEC
Ethernet MAC IP
- The Synopsys 1.6T Ethernet MAC IP is based on IEEE 802.3-2018 spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications
- Synopsys 1.6T Ethernet MAC IP
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
- 100G Ethernet MAC/RS
- 800G/400G/200G Ethernet MAC
- 40G/100G Ethernet PCS/MAC IP Cores