MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
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25G Ethernet MAC and PCS + RS-FEC
The 25G Ethernet MAC & PCS + RS-FEC is compliant with IEEE802.3by -2016 and 25/50G Ethernet Consortium specifications. The core is designed using advanced design techniques leading to unmatched ultra-low gate count utilization and great latency performances. It includes a rich set of standard and advanced features making it ideal for a large number of applications.
The IP core can support full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.
The core includes Reed Solomon FEC RS(528, 514, 10) with FEC bypass and error correction bypass capabilities. A second option of the IP core without RS-FEC is also available.
The IP core can support full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.
The core includes Reed Solomon FEC RS(528, 514, 10) with FEC bypass and error correction bypass capabilities. A second option of the IP core without RS-FEC is also available.
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Block Diagram of the 25G Ethernet MAC and PCS + RS-FEC
