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25-Gbps Ultra-Low Latency Ethernet MAC & PCS + RS-FEC

The 25G Ethernet MAC & PCS + RS-FEC is compliant with IEEE802.3by-2016 and 25/50G Ethernet Consortium specifications. The core is designed using advanced design techniques leading to unmatched ultra-low gate count utilization and great latency performances. It includes a rich set of standard and advanced features making it ideal for a large number of applications.

The IP core can support full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.

The core includes Reed Solomon FEC RS(528, 514, 10) with FEC bypass and error correction bypass capabilities. A second option of the IP core without RS-FEC is also available.

特色

General Features

Compliant with IEEE802.3by-2016 and 25/50G Ethernet Consortium
Ethernet MAC supports 25GbE line rate with flexible feature set
Soft PCS logic interfacing to standard serial transceiver at 25.78125Gbps

MAC Features

Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average
Programmable IPG length
Programmable Maximum Receive Unit (MRU), Maximum Transmission Unit (MTU)
User facing logic interface 64-bit @ ~402.8MHz
Ethernet flow control and congestion management using pause frames with programmable quanta
XON / XOFF Frame transmission can be triggered by host (software) interface or directly by core pause frame interface signals
Programmable Tx minimum packet length with enable/disable padding option
Programmable Rx minimum packet length
Tx Frame Check Sequence (FCS) computation and insertion
Programmable Tx FCS pass-through and corruption insertion modes
Programmable keep/strip Rx FCS. Programmable Rx FCS error detection and marking
Programmable Tx and Rx large frame threshold detection
Programmable Tx and Rx path VLAN detection (Programmable TPID, stacked VLAN)
Programmable Rx frame discard & marking
Configurable statistics vector and collector on transmit and receive MAC data

PCS Features

Supports 25GBASE-R PHY based on 64B/66B encoding and scrambling
Supports block synchronization and BER monitor
Configurable statistics vector and collector on transmit and receive PCS

RS-FEC Features

Built-In Reed Solomon FEC RS(528, 514, 10) with FEC bypass and error correction bypass capabilities
Pre-compilation setting to include or not RS-FEC option (MAC/PCS/PMA or MAC/PCS/PMA + RS-FEC)
Statistics information for RS-FEC decoder (FEC align status, corrected & uncorrected FEC codewords)

应用

The Ultra-Low Latency Ethernet MAC & PCS IP cores are based on cut-through architecture and innovative FCS processing algorithms resulting in amazing latency performances. Typical applications where latency is critical: