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224G Ethernet PHY for TSMC 3nm
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurement techniques, the Synopsys 224G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3 and OIF standards electrical specifications. The area efficient PHY provides additional margin for channel loss and demonstrates zero post-FEC BER.
The PHY supports the Pulse-Amplitude Modulation 4 (PAM-4) and Non- Return-to-Zero (NRZ) signaling to deliver up to 1.6T Ethernet. The configurable transmitter and advanced DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The Continuous Calibration and Adaptation (CCA) algorithm provides robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance.
The PHY has been co-designed and optimized with the Synopsys Physical Coding Sublayer (PCS) and Media Access Controller (MAC) IP to reduce integration time and provide solution level differentiation.
Combined with Synopsys’ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 224G Ethernet PHY solution for fast and reliable SoC integration and first pass silicon success.
The PHY supports the Pulse-Amplitude Modulation 4 (PAM-4) and Non- Return-to-Zero (NRZ) signaling to deliver up to 1.6T Ethernet. The configurable transmitter and advanced DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The Continuous Calibration and Adaptation (CCA) algorithm provides robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance.
The PHY has been co-designed and optimized with the Synopsys Physical Coding Sublayer (PCS) and Media Access Controller (MAC) IP to reduce integration time and provide solution level differentiation.
Combined with Synopsys’ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 224G Ethernet PHY solution for fast and reliable SoC integration and first pass silicon success.
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