224G Ethernet PHY for TSMC 3nm
The PHY supports the Pulse-Amplitude Modulation 4 (PAM-4) and Non- Return-to-Zero (NRZ) signaling to deliver up to 1.6T Ethernet. The configurable transmitter and advanced DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The Continuous Calibration and Adaptation (CCA) algorithm provides robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance.
The PHY has been co-designed and optimized with the Synopsys Physical Coding Sublayer (PCS) and Media Access Controller (MAC) IP to reduce integration time and provide solution level differentiation.
Combined with Synopsys’ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 224G Ethernet PHY solution for fast and reliable SoC integration and first pass silicon success.
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224G Ethernet PHY IP
- 224G Ethernet PHY in TSMC (N3E)
- 224G Ethernet PHY IP for TSMC N3E
- The Synopsys 1.6T Ethernet MAC IP is based on IEEE 802.3-2018 spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications
- The Synopsys 1.6T Ethernet PCS IP is based on the IEEE 802.3dj spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications
- Synopsys 1.6T Ethernet MAC IP
- 1.6T Ethernet PCS IP