MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
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20GSa/s 12-Bit Analogue-to-Digital Converter (ADC)
1-VIA’s high-speed low-power RF-ADC is targeted at upcoming telecommunication markets such as 5G and Satellite Communications. The RF-ADC has an effective 3dB bandwidth > 9GHz and 10 Effective Number of Bits (ENOB), making it an ideal candidate for FR1 (sub-6 GHz) and FR2 (mmWave 6-100 GHz) 5G deployment scenarios.
The ADC is a standalone macro which employs calibration of time interleaving skew, linearity and offset both at start-up and continuously in the background.
The ADC is a standalone macro which employs calibration of time interleaving skew, linearity and offset both at start-up and continuously in the background.
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Block Diagram of the 20GSa/s 12-Bit Analogue-to-Digital Converter (ADC)
