The Xelic 2x200/400 Gigabit Ethernet OPU Mapper Core (XCOC24M) performs PCS fault monitoring/insertion, RMON binning, RC Block insertion/extraction, optional pause-frame insertion (de-map direction), and the scramble/descramble function required to map/demap 2x200/400 GE to/from an ODUflex payload using an optimized timesliced architecture. The XCOC24M contains independent PCS Mapper and PCS Demapper blocks. This core is instantiated between the XCOC24BSFEC and the XCOC24Flex. The datapath input and output to this core is a simple 66b PCS stream. The client side interface that connects to the XCOC24BSFEC is 1320-bits wide (66*20) and the line-side interface that connects to the XCOC24Flex is 1280-bits wide (64*20). The data on the client interface will always be aligned such that a 66-bit PCS block will align to the top of the bus. Both interfaces are clocked by an overclocked system clock with push through data-valid signaling. This core is expected to operate at a clock rate between 332.1MHz and 360MHz.
The XCOC24M implements a generic register interface for access and configuration of internal memory mapped register locations. This interface is shared between PCS Mapper and PCS Demapper with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.