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Frequency synthesizer 20÷300MHz - SilTerra 0.18um
The system generates stable clock signal with frequency from 20 to 300 MHz. The synthesizer is based on an integer Phase Locked Loop (PLL).
Input ckref is connected to reference clock signal with frequency from 8 to 16 MHz. Output pll_clk is signal with desired frequency.
Input ckref is connected to reference clock signal with frequency from 8 to 16 MHz. Output pll_clk is signal with desired frequency.
查看 20 to 300 MHz frequency synthesizer 详细介绍:
- 查看 20 to 300 MHz frequency synthesizer 完整数据手册
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20 to 300MHz frequency synthesizer IP
- PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process
- PLL (Frequency Synthesizer) IP, Input: 5MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.15um SP process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
- PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 20MHz - 300MHz, UMC 0.18um G2 process
- PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 65nm LL process
- Frequency synthesizer 20 to 300 MHz