IFA consist of 3-stages amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-digital converter for digital output and output level detector.
Each stage of the amplifier has differential input and output. Gain is sequentially reduced from the last stage to the first stage for better noise performance in wide gain range.
Output voltage supported by AGC system:
- For sine waveform 200 mV (peak-to-peak)
- For noise signal 480 mV (peak-to-peak)
The block is fabricated on TSMC SiGe BiCMOS 180 nm technology.
- TSMC SiGe BiCMOS 180nm
- Wide gain range (0…66 dB)
- Low group delay time ripple vs. frequency and gain
- Analog and digital output modes
- Automatic gain control (AGC) system
- DC offset compensation in each amplifier stage and output buffer
- AGC detector threshold adjustment in the digital mode
- Analog-digital converter to produce digital output signal
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, SilTerra
- Schematic or NetList
- Abstract view (.lef and .lib files)
- Layout (optional)
- Verilog behavior model
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- IF signal amplification
- GNSS receiver