The voltage regulator consists of a differential amplifier, pass transistor and resistor's divider. Differential amplifier compares reference voltage with voltage from a feedback divider and adjusts the impedance of a PMOS transistor for stabilization of output voltage at a set level. The output voltage adjustment is defined by the trimming code trim<5:0>. The block has low supply current and allows high current load.
The LDO can operate in two modes: “Normal” and “Economy”. “Economy” mode is introduced to save battery power. Although the mode may handle full current load, it has slower reactions on load current change. “Normal” mode is a default LDO mode with minimum response time on load change.
The block is designed on Global Foundries CMOS 55 nm technology.
- Global Foundries CMOS 55 nm
- Low drop out
- Low current consumption
- Two modes operations: “Normal”, “Economy”
- No discrete filtering capacitors required (cap-less solution)
- Output voltage trimming
- Small area
- Supported foundries: TSMC, UMC, SMIC, iHP, AMS, Vanguard, SilTerra, X-FAB
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Supply voltage sensitive circuits