You are here:
2-bit 1-channel 50 MHz flash ADC
The circuit is 2-bit ADC with programmable threshold. Least significant bit, calling sign bit, turns to 1 or 0 with changing of differential input signal’s polarity. Most significant bit, calling magnitude bit, turns to 1 if there is an excess of the threshold by differential input signal.
The block consists of:
Reference voltages and currents source:
3 asynchronous comparators represent the core of ADC
Offset compensation system
Clocking signal system
Logical “1” level convertor from 1.8 V to 3 V
The chose of a threshold is carried by external 3-bit binary code at input lvl in range from 48 mV to 97 mV (table 1). Input signal passes through emitter followers passes to 3 comparators: sign comparator and two magnitude comparators. There is logical “1” at sign output for positive polarity, and logical “1” at magn output if signal excesses the threshold level. Outputs of comparators are fed to clocking system.
There are two working modes of clocking system: asynchronous mode and clocking mode. In asynchronous mode the output signals of comparators are fed directly to output powerful CMOS-buffers, which working for PADs. The CMOS-buffers have separate supply voltage 3 V or 1.8 V, so the logical “1” level of output signal could be 3 V or 1.8 V. In clocking mode the output signals are strobed by external ECL-clocking signal, which is converted to CMOS-signal by in-built ECL-to-CMOS buffer.
The offset compensation system works by output signals of powerful digital buffers. These signals are fed from PADs to logical level converter (from 1.8 V to 3 V), which is necessary while working for 1.8 V supply voltage. The offset compensation system itself is an integrating cascade, accumulating the offset error and shifting the common mode level of comparators’ input signal to compensate the error
The block consists of:
Reference voltages and currents source:
3 asynchronous comparators represent the core of ADC
Offset compensation system
Clocking signal system
Logical “1” level convertor from 1.8 V to 3 V
The chose of a threshold is carried by external 3-bit binary code at input lvl in range from 48 mV to 97 mV (table 1). Input signal passes through emitter followers passes to 3 comparators: sign comparator and two magnitude comparators. There is logical “1” at sign output for positive polarity, and logical “1” at magn output if signal excesses the threshold level. Outputs of comparators are fed to clocking system.
There are two working modes of clocking system: asynchronous mode and clocking mode. In asynchronous mode the output signals of comparators are fed directly to output powerful CMOS-buffers, which working for PADs. The CMOS-buffers have separate supply voltage 3 V or 1.8 V, so the logical “1” level of output signal could be 3 V or 1.8 V. In clocking mode the output signals are strobed by external ECL-clocking signal, which is converted to CMOS-signal by in-built ECL-to-CMOS buffer.
The offset compensation system works by output signals of powerful digital buffers. These signals are fed from PADs to logical level converter (from 1.8 V to 3 V), which is necessary while working for 1.8 V supply voltage. The offset compensation system itself is an integrating cascade, accumulating the offset error and shifting the common mode level of comparators’ input signal to compensate the error
查看 2-bit 1-channel 50 MHz flash ADC 详细介绍：
- 查看 2-bit 1-channel 50 MHz flash ADC 完整数据手册
- 联系 2-bit 1-channel 50 MHz flash ADC 供应商