You are here:
2.8GHz to 3.3GHz Fractional-N Phase-Locked Loop
PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multiplied by a given integer. Frequency adjustment is carried out by using negative feedback. A phase detector compares a controlled oscillator output with a reference signal. The result is a charge pump current output that supplies external feedback filter and converted to a voltage for controlled oscillator adjustment. Clock divider is used to generate signals with specified frequency. Delta-sigma modulator makes it possible to operate with reference oscillator of different frequency.
The block is fabricated on SMIC CMOS 0.18 um technology.
The block is fabricated on SMIC CMOS 0.18 um technology.
查看 2.8GHz to 3.3GHz Fractional-N Phase-Locked Loop 详细介绍：
- 查看 2.8GHz to 3.3GHz Fractional-N Phase-Locked Loop 完整数据手册
- 联系 2.8GHz to 3.3GHz Fractional-N Phase-Locked Loop 供应商
PLL IP
- TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
- TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL
- TSMC GF Intel Samsung Fractional-N Frequency Synthesizer PLL
- TSMC GF Intel Samsung Integer-N Frequency Synthesizer PLL
- Jitter Cleaner PLL Digital Loop Filter
- TSMC Intel 32kHz Low-bandwidth Frequency Synthesizer PLL