MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
2.5V Secondary Oxide DDRx/LPDDRx PHY - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF - 1.8V UMC 40ULP
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