MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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2.5G MIPI D-PHY in TSMC 22nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specification for MIPI D-PHY rev1.2 with speeds up to 2.5 Gbps per lane in 28nm or 22nm logic process node, this ACTT Design IP of MIPI D-PHY supports DSI/DSI-2 and CSI-2 protocols.
These IPs is a mixed-signal PHY consisting of a DSI D-PHY transmitter and a DSI D-PHY receiver. The PHY IP is designed to be robust under varying signal strength and noise conditions.
The PHY IP is part of the comprehensive ACTT Design IP portfolio comprised of high speed interface, memory, low power analog, and system IPs.
These IPs is a mixed-signal PHY consisting of a DSI D-PHY transmitter and a DSI D-PHY receiver. The PHY IP is designed to be robust under varying signal strength and noise conditions.
The PHY IP is part of the comprehensive ACTT Design IP portfolio comprised of high speed interface, memory, low power analog, and system IPs.
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