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1G/10G/25G/50G/100G Ethernet Switch IP Core - Efficient and Massively Customizable
Packet Architects offers a series of high speed switching IP cores, developed using the unique FlexSwitch toolchain. This toolchain provides a fast and flexible development environment for switching/routing IP cores for any packet based technology.
This Ethernet Switch IP core offers a full range of features and wirespeed throughput on all ports, one of which can be configured as a high speed CPU port. Each port has a number of priority queues controlled by a strict priority scheduler. This allows the most timing critical packets to get minimal delay while providing fairness between queues.
The switch is built around a shared buffer memory architecture supporting wirespeed switching on all ports without head of line blocking. It offers dynamic allocation of packet buffering per port and priority to avoid starvation due to over-allocation. The switching core also features multiple VLAN tagging and untagging operations, along with egress VLAN translation.
A processor interface allows setup of tables and registers. There is also a packet-based CPU port for packets to and from the CPU.
This IP core requires no software setup, and it has hardware learning for MAC addresses. Thus it is ready to receive and forward Ethernet frames immediately once powered up.
This Ethernet Switch IP core offers a full range of features and wirespeed throughput on all ports, one of which can be configured as a high speed CPU port. Each port has a number of priority queues controlled by a strict priority scheduler. This allows the most timing critical packets to get minimal delay while providing fairness between queues.
The switch is built around a shared buffer memory architecture supporting wirespeed switching on all ports without head of line blocking. It offers dynamic allocation of packet buffering per port and priority to avoid starvation due to over-allocation. The switching core also features multiple VLAN tagging and untagging operations, along with egress VLAN translation.
A processor interface allows setup of tables and registers. There is also a packet-based CPU port for packets to and from the CPU.
This IP core requires no software setup, and it has hardware learning for MAC addresses. Thus it is ready to receive and forward Ethernet frames immediately once powered up.
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