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16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provide optimization of power, performance and area to meet the growing needs for high bandwidth and low latency in the applications of consumer, access layer networking device to core/enterprise layer.
The silicon verified 16Gbps SerDes PHY supports the optimization of SoC chip designs to enable the infrastructure of 10G/40G Ethernet, PCIe 4.0, 5G, and most xPON applications. Compared with the other latest Serdes solutions, it is the only solution that supports both PCIe 4.0 and 10G xPON ONU/OLT in 28nm node.
This full-duplex, high-performance and many-protocols compatible SerDes solution comes with a scalable PMA which can be applied to a wide range of applications across copper and backplane channels with total insertion loss more than 30dB. It is also compatible with standard PCS and controller, and provides flexible design environment for users to customize PCS and controller integration.
The silicon verified 16Gbps SerDes PHY supports the optimization of SoC chip designs to enable the infrastructure of 10G/40G Ethernet, PCIe 4.0, 5G, and most xPON applications. Compared with the other latest Serdes solutions, it is the only solution that supports both PCIe 4.0 and 10G xPON ONU/OLT in 28nm node.
This full-duplex, high-performance and many-protocols compatible SerDes solution comes with a scalable PMA which can be applied to a wide range of applications across copper and backplane channels with total insertion loss more than 30dB. It is also compatible with standard PCS and controller, and provides flexible design environment for users to customize PCS and controller integration.
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Block Diagram of the 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
