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12G PHY in TSMC (28nm, 16nm, 12nm)
The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys’ high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the Enterprise 12G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards’ electrical specifications. The PHY is small in area and provides a low-power, cost-effective solution that supports multiple industry standards to meet the needs of applications with high-speed port side, chip-to-chip, board-to-board, and backplane interfaces.
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive. The embedded BER tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare® Physical Sublayer cores and the digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.These features reduce both product development cycles and the need for costly field support.
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive. The embedded BER tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare® Physical Sublayer cores and the digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.These features reduce both product development cycles and the need for costly field support.
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PCI Express PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 5.0 PHY in TSMC (16nm)
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe4 Ethernet SERDES PHY - TSMC N5