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12bit +20Gsps Low power and Low area silicon proven Cap-less channel in 16nm ADC
Silicon proven in TSMC 16nm CMOS process, this is an ultra-high speed, ultra-high performance Current Steering ADC IP core.The ADC achieves low noise and excellent SFDR in a compact area. For ease of integration, an integrated reference buffer is included.
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Block Diagram of the 12bit +20Gsps Low power and Low area silicon proven Cap-less channel in 16nm ADC
ADC/DAC IP
- 24bit Audio ADC/24bit Video DAC
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- 90 dB of SNR, 24-bit mono audio ADC, stereo audio DAC with capless headphone driver
- Audio CODEC with 100 dB Dynamic Range, 24-bit stereo PWM DAC, six-channel ADC
- Audio codec with capacitor-less 106 dB dynamic range ADC and 100 dB DAC with very low latency filters
- Audio codec with capacitor-less 104 dB dynamic range ADC and 100 dB DAC