12bit, 1.6GSPS Ultra Low Power ADC - TSMC 7nm
This 12-bit, 1.6GSPS ADC supports input signals up to 800 MHz and features a differential full-scale range of 1Vpp and excellent static and dynamic performance.
The ADC architecture is optimized to maximize performance while minimizing power and area consumption. The ADC input is buffered by an optional input buffer and then distributed to time-interleaved ADC channels.
The ADC includes built in calibration to remove time interleaving artifacts, including offset mismatch, gain mismatch and timing skew.
To maximize SNR, the ADC includes an ultra-low-jitter clock distribution network with aperture jitter of 100fsrms.
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