12-bit 800 kSPS cascade delta-sigma ADC
Two delta-sigma modulators second and first order, coupled in series and combined by noise cancellation logic
Clock splitter
Block of bias currents, tunable (3-bit control)
DWA-correction of capacitors’ mismatch
Input signal level detection
Output signal is represented in thermometer code at the output of each stage. There is a possibility to disable the second stage of modulator, DWA correction. Tuning of bias current for operational amplifiers with 3-bit control included.
Common mode voltage - 0.9 V; recommended values of reference voltages: 0.9 ± 0.4 V; recommended differential input signal amplitude - 0.64 V; allowable duty cycle: 50 ± 5%.
The block is designed on TSMC BiCMOS SiGe 180 nm technology.
特色
- TSMC 180 nm BiCMOS SiGe technology
- Wideband cascade (2-1) delta-sigma ADC
- 12-bit resolution
- Operational amplifiers’ current adjustment
- Supply voltage - 1.8 V
- Input signal range 1.6 V (differential peak-to-peak)
- In-built input signal level detection, sign detection
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra, X-FAB
可交付内容
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
应用
- Analog to digital conversion of wide-band signal
- Receivers, transceivers
- Analog integral circuits
- Measurement environment
- Medicine environment
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