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12-bit 800 kSPS cascade delta-sigma ADC
The block is third order cascade (2-1) delta-sigma ADC with 5-level quantizers in both stages. The block consists of:
Two delta-sigma modulators second and first order, coupled in series and combined by noise cancellation logic
Clock splitter
Block of bias currents, tunable (3-bit control)
DWA-correction of capacitors’ mismatch
Input signal level detection
Output signal is represented in thermometer code at the output of each stage. There is a possibility to disable the second stage of modulator, DWA correction. Tuning of bias current for operational amplifiers with 3-bit control included.
Common mode voltage - 0.9 V; recommended values of reference voltages: 0.9 ± 0.4 V; recommended differential input signal amplitude - 0.64 V; allowable duty cycle: 50 ± 5%.
The block is designed on TSMC BiCMOS SiGe 180 nm technology.
Two delta-sigma modulators second and first order, coupled in series and combined by noise cancellation logic
Clock splitter
Block of bias currents, tunable (3-bit control)
DWA-correction of capacitors’ mismatch
Input signal level detection
Output signal is represented in thermometer code at the output of each stage. There is a possibility to disable the second stage of modulator, DWA correction. Tuning of bias current for operational amplifiers with 3-bit control included.
Common mode voltage - 0.9 V; recommended values of reference voltages: 0.9 ± 0.4 V; recommended differential input signal amplitude - 0.64 V; allowable duty cycle: 50 ± 5%.
The block is designed on TSMC BiCMOS SiGe 180 nm technology.
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