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12-Bit 320MS/s Dual Current Steering DAC
The S3DAIQ320M12BGF28SLP employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 12-bit Dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±2.0LSB INL for typical conditions.
Dynamic performance highlights considering a signal frequency of 10MHz and 320MS/s conversion rate include an SNR= 69dB and an SFDR=70dBc.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 12-bit Dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±2.0LSB INL for typical conditions.
Dynamic performance highlights considering a signal frequency of 10MHz and 320MS/s conversion rate include an SNR= 69dB and an SFDR=70dBc.
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Block Diagram of the 12-Bit 320MS/s Dual Current Steering DAC
