The S3DAIQ320M12BT40LP employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
- 40nm TSMC LP Process, 6 Metals Used
- 2.5V and 1.1V Supplies
- Sampling Rate up to 320MS/s
- 1.0Vpp Differential Output Range
- DNL= 0.5LSB; INL<1.0LSB.Typ
- High Performance for Fout=10MHz
- SNR= 68dB, SFDR=71dB
- In-band SFDR=75dB with Fout=10MHz
- Stand-By and Power-Down Modes
- 24mW Power Consumption at 4mA output current
- Compact Die Area pre-shrink: 0.25mm2
- This 12-bit Dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL for typical conditions.
- Dynamic performance highlights considering a signal frequency of 10MHz and 320MS/s conversion rate include an SNR= 68dB and an SFDR=71dBc.
- The S3DAIQ320M12BT40LP is designed for operation up to 320MS/s. The S3DAIQ320M12BT40LP is designed in a 40nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
- WiFi 802.11x, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12位320MS/s 双通道DAC