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来自于S3 Group应用于IoT/WiFi/WiMax, 有线通信以及数字合成的12位DAC。

The S3DAIQ20M12BSM55LL employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.

This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture and randomization of the output current sources.

The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.

特色

55nm SMIC eFlash Process, 6 Metals Used
1.8V and 1.2V Supplies
Sampling Rate up to 20MS/s
1.0Vpp Differential Output Range
DNL< 1.0LSB; INL<2.0LSB.
High Performance for Fout=50kHz
SNR > 70dB, SFDR > 70dB
6mW Power consumption at 0.5mA Output current
Stand-By and Power-Down Modes
Die Area post-shrink: 0.3mm2

优势

This 12-bit Dual DAC features an excellent static performance that includes ±0.8LSB DNL and ±1.5LSB INL for typical conditions.
A bias/bandgap is included for easy integration. Dynamic performance highlights considering a signal frequency of 50KHz and 20MS/s conversion rate include an SNR > 70dB and an SFDR > 70dBc.
The S3DAIQ20M12BSM55LL is designed for operation up to 20MS/s. The S3DAIQ20M12BSM55LL is designed in a 55nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.