12-bit 50MS/s Dual Current Steering DAC contains two DAC core, Reference current, Bandgap. Core DAC is based on current steering architecture and contain Control logic, Current source and switches array and reference voltage. There are two operating mode with external reference current and internal reference current, which independent from voltage supply, temperature and dependent from process of resistor. DAC has a feature of adjusting output current. A segmented DAC architecture and Q2 Random Walk algorithm are used. DACs requires: 3.0 ÷ 3.6 V analog supply, 3.0 ÷ 3.6 V digital supply, differential input clock with duty cycle 45 ÷ 55%. 12-bit 50 MS/s dual current seering DAC supports standby mode.
The block is designed on TSMC CMOS 180 nm technology.