The S3ADS160MD12BSM28SP is an ultra low-power 12-bit dual-channel high-speed SAR ADC IP with a core sampling frequency up to 160MS/s.
For maximum application flexibility, the power dissipation of this ADC scales with the sampling rate. This 12-bit ADC can be used in single-channel mode or dual-channel mode allowing for I/Q operation. It features an excellent cross-channel performance that includes 0.1dB gain mismatch and -80dB crosstalk between channels.
Considering a dual-channel operation at a sampling rate of 80MS/s per channel, a 10MHz input frequency and an input range of 1Vppdiff, this ADC IP features an outstanding dynamic performance that includes 76dB SFDR, -75dB THD, 63.5dB SNR and 10.2-bit ENOB.
The S3ADS160MD12BSM28SP does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.
- SMIC 28nm PolySiON (SP) Process
- No Analog Options
- 1.05V Core & 1.8V I/O Supplies
- 12-bit ADC, High-Speed SAR-based Architecture
- Differential Input Signal Range: 1.0Vppdiff
- Single Channel or Dual-Channel Operation
- Single-Channel Max Sampling Rate: 160MS/s
- Dual-Channel Max Sampling Rate: 80MS/s per Ch.
- Power Consumption Scaling with Frequency
- Internal Bandgap and Biasing System
- All Required Voltage References Included
- Outstanding Dynamic Performance
- 76dB SFDR at fin=10MHz
- -75dB THD at fin=10MHz
- 63.5dB SNR at fin=10MHz
- 63.1dB SNDR at fin=10MHz
- 10.2-bit ENOB at fin=10MHz
- [Noise integrated from DC to Nyquist]
- Outstanding Cross-Channel Performance:
- 0.1dB Channels Gain Mismatch
- -80.0dB Crosstalk between Channels
- Stand-by and Power Down Modes
- Ultra Low Power Dissipation:
- Ultra Efficient ADC Converter:
- DVB – S/T/C/S2/T2
- PLC, DOCSIS, MoCA
Block Diagram of the 12-bit 160MS/s Ultra-Efficient Dual-Input ADC