Rambus DPA Resistant Cryptographic Accelerator Core ChaCha20 – Small
12-bit 15-to-122MS/s Ultra-Efficient Dual-Input ADC
For maximum application flexibility, the power dissipation of this ADC scales with the sampling rate. This 12-bit ADC can be used in single-channel mode or dual-channel mode allowing for I/Q operation. It features an excellent cross-channel performance that includes 0.1dB gain mismatch and -80dB crosstalk between channels.
Considering a dual-channel operation at maximum sampling rate of 61.44MS/s per channel, a 10MHz input frequency and an input range of 1Vppdiff, this ADC IP features an outstanding dynamic performance that includes 76dB SFDR, -75dB THD, 63.5dB SNR and 10.2-bit ENOB.
This high-end performance is obtained while dissipating a mere 8mW for the complete ADC solution including internal reference voltage generation. That corresponds to an ultra-efficient figure of merit of only 55fJ per converted sample per channel.
The 12-bit 15-to-122MS/s Dual-Input ADC does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.
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Block Diagram of the 12-bit 15-to-122MS/s Ultra-Efficient Dual-Input ADC

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