The 12-bit 15-to-122MS/s Dual-Input ADC is an ultra low-power 12-bit dual-channel high-speed SAR ADC IP with a core sampling frequency ranging from 15.36MS/s up to 122.88MS/s.
For maximum application flexibility, the power dissipation of this ADC scales with the sampling rate. This 12-bit ADC can be used in single-channel mode or dual-channel mode allowing for I/Q operation. It features an excellent cross-channel performance that includes 0.1dB gain mismatch and -80dB crosstalk between channels.
Considering a dual-channel operation at maximum sampling rate of 61.44MS/s per channel, a 10MHz input frequency and an input range of 1Vppdiff, this ADC IP features an outstanding dynamic performance that includes 76dB SFDR, -75dB THD, 63.5dB SNR and 10.2-bit ENOB.
This high-end performance is obtained while dissipating a mere 8mW for the complete ADC solution including internal reference voltage generation. That corresponds to an ultra-efficient figure of merit of only 55fJ per converted sample per channel.
The 12-bit 15-to-122MS/s Dual-Input ADC does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.
- TSMC 40nm Low Power (LP) Process
- 6 Metals Only
- No Analog Options
- 1.1V Core & 2.5V I/O Supplies
- 12-bit ADC, High-Speed SAR-based Architecture
- Differential Input Signal Range: 1.0Vppdiff
- Single Channel or Dual-Channel Operation
- Core Sampling Rate from 15.36MS/s up to 122.88MS/s
- Single-Channel Max Sampling Rate: 122.88MS/s
- Dual-Channel Max Sampling Rate: 61.44MS/s per Ch.
- Power Consumption Scaling with Frequency
- Internal Bandgap and Biasing System
- All Required Voltage References Included
- Outstanding Dynamic Performance
- 76dB SFDR at fin=10MHz
- -75dB THD at fin=10MHz
- 63.5dB SNR at fin=10MHz
- 63.1dB SNDR at fin=10MHz
- 10.2-bit ENOB at fin=10MHz
- [Noise integrated from DC to Nyquist]
- Outstanding Cross-Channel Performance:
- 0.1dB Channels Gain Mismatch
- -80.0dB Crosstalk between Channels
- Stand-by and Power Down Modes
- Ultra Low Power Dissipation:
- Only 8mW Including References, Dual Channel Mode at Max Rate
- Only 5mW Excluding References, Dual Channel Mode at Max Rate
- Ultra Efficient ADC Converter:
- Ultra Compact Die Area
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Integration Support
- Connected Consumer Devices
- Wireline Communications
Block Diagram of the 12-bit 15-to-122MS/s Ultra-Efficient Dual-Input ADC