The low-power high-speed 12-bit ADC employs a high-performance differential pipeline architecture.
The ADC consists of a core ADC, output logic, timing generation, reference currents circuits. The ADC requires: 1.08 ÷ 1.32 V analog supply, 1.08 ÷ 1.32 V digital supply, differential reference voltages 0.85 V and 0.35 V, common mode voltage 0.6 V, reference current 9.9 ÷ 10.1 uA and differential input clock.
The ADC supports standby mode which allows state with minimum power consumption.
There is also the ability to configure the operating modes of the ADC by using digital registers.
The block is designed on TSMC CMOS 65 nm technology.