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12-bit 1.2GSps High-Dynamic Performance DAC in 40nm CMOS
This high-speed Digital-to-Analog Converter (DAC) IP block is implemented with fully differential single channel output specifically designed for crystal drivers and wideband signal handling.
The 12-bit DAC is based on current steering architecture and utilizes segmentation and robust timing control for high-speed operation till 1.2GSps. Typical DAC SFDR is 71dB for a 42MHz output frequency with 67dB of SNR.
Using a small geometry CMOS process, the monolithic DAC is designed to operate within a single-supply range of 1.6V to 3.3V. It provides programmable control to tune the output current range and power consumption.
The 12-bit DAC is based on current steering architecture and utilizes segmentation and robust timing control for high-speed operation till 1.2GSps. Typical DAC SFDR is 71dB for a 42MHz output frequency with 67dB of SNR.
Using a small geometry CMOS process, the monolithic DAC is designed to operate within a single-supply range of 1.6V to 3.3V. It provides programmable control to tune the output current range and power consumption.
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