The S3DA1G12BT28HPCP employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
- 28nm TSMC HPC+ Process, 7 Metals Used
- (No Analog Options)
- 1.8V and 0.9V Supplies
- Sampling Rate up to 1250MS/s
- 1.0Vpp Differential Output Range
- Programmable full-scale current possible 5-20mA
- Performance for Fout<150MHz
- SFDR > 63dBc,ENOB>10.0bits
- MTPR 57dB up to 298MHz @ PAPR=15dB
- Stand-By and Power-Down Modes
- Compact Die Core Area: 0.22mm2
- The 12-bit DAC dynamic performance highlights considering a signal frequency of 150MHz and 1250MS/s conversion rate include an SNDR > 62dB and an SFDR > 63dBc.
- The S3DA1G12BT28HPCP is designed in a 28nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (verilog)
- Integration Support
- Next Generation DSL
- Wireline Communications
- Wireless Communications
Block Diagram of the 应用于高速有线和无线通信的 12位1.25GS/s DAC