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112G LR Multi-protocol SerDes PHY

An ADC-based long-reach (LR) 112G SerDes PHY solution providing leading-edge performance and power efficiency for next-generation networking and hyperscale data center applications.

The Rambus 112G LR Multi-Protocol SerDes (MPS) PHY is a comprehensive IP solution designed to provide best-in-class performance across challenging long reach signaling environments for next-generation networking applications. The 112G MPS PHY supports PAM-4 and NRZ signaling and data rates from 10.3 to 106.25 Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the PHY architecture is an ADC operating at 56 GS/s that allows for adjustable power and improved performance while providing low BER.

特色

Supports up to 4 duplex lanes and data rates from 10.3 to 106 Gbps
Embedded micro-processor enables firmware-controlled PMA configuration, initialization and adaptation for maximum flexibility and minimum ASIC integration effort
RX front end with on-chip capacitors supports both AC-coupled and DC-coupled channels
Configurable architecture enables power saving models for low and medium loss channels
Programmable TX/RX equalizers including: ·· Multi-tap digital FFE and DFE for extended channel reach
A centralized LC-PLL supports a wide range of reference clock frequencies and lane operating frequencies
Differential reference clock inputs selectively sourced from dedicated pins or internal ASIC interface pins
Direct register control available for all PMA functions
Flexible layout supports placement along all ASIC edges in an ASIC
PMA is spec compliant across a wide operating junction temperature range (-20 °C to 105 °C). PLLs, bias circuits, and data paths are functional between -40 °C to 125 °C
In-situ real-time monitoring and receive data eye voltage histogram
Built in PRBS generators and checkers along with custom pattern generation
ATPG Mux Scan support for digital logic
IEEE 1149.6 JTAG boundary scan for SerDes pins
Built-in BER monitor including a 40-bit counter to count the total number of bits received and a 30-bit counter to count the total number of errors detected by a pattern checker
Internal serial loopback and parallel loopback support
Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
Analog and digital test bus

优势

Duplex lane configurations of x2, x4, and x8
Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mV for SR
Support for AC-coupled interfaces
Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and GbE protocols
A wide range of PLL multiplication supporting low reference clock frequencies
Flexible ASIC clocking
Tight skew control of 2UI between lanes of the PMA
3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
8-tap Rx DFE (Decision Feedback Equalizer)
Second-order CDR meeting SSC and RX sinusoidal jitter requirements
Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
Built-in PRBS pattern generation and checking for standalone loopback testing
In-situ real-time monitoring and receive data eye schmoo
Operation across a wide temperature range (-40 C to +125 C)