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112G LR-Max Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient PHY provides a low active and standby power solution that supports multiple electrical standards, including PCI Express® (PCIe®) 6.0, 1G to 112Gbps electrical PHY for 400G/800G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), JESD204C, CPRI, SATA, and other
industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 112G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The multi-protocol 112G PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitorprovide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) for 200G/400G/800G links to deliver a complete solution, reduce design time and help designers achieve first-pass silicon success.
industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 112G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The multi-protocol 112G PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitorprovide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) for 200G/400G/800G links to deliver a complete solution, reduce design time and help designers achieve first-pass silicon success.
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Video Demo of the 112G LR-Max Ethernet PHY for TSMC N5
This TSMC Symposium 2022 demo shows the Synopsys 112G Ethernet PHY IP for long reach successfully interoperating with Amphenol's 2m DAC cable system and showing BER that's seven orders of magnitude better than the specification.